论文标题
卷曲：智能和无缝设计的智能边缘处理器的设计
CONVOLVE: Smart and seamless design of smart edge processors
论文作者
论文摘要
随着深度学习的兴起（DL），我们的世界在每个边缘设备中为AI提供了牙套，从而迫切需要对边缘ai socs。该SOC硬件需要在超低功率（ULP）上支持高吞吐量，可靠和安全的AI处理，并在很短的时间内进行营销。欧盟凭借其在Edge解决方案和开放处理平台方面的强大遗产，因此在这一SOC市场中成为领导者。但是，这需要AI边缘处理至少增加100倍的节能，同时提供足够的灵活性和可扩展性来处理AI作为快速移动的目标。由于这些复杂的Soc的设计空间很大，因此需要高级工具才能使其设计可进行。卷积项目（目前处于艰巨的阶段）解决了这些障碍。在设计层次结构的各个层面上，它采用了整体方法。从SOTA DL处理支持和我们的项目方法的概述开始，本文介绍了8重要的设计选择在很大程度上影响了DL硬件的能源效率和灵活性。找到好的解决方案是使智能边缘计算成为现实的关键。
With the rise of Deep Learning (DL), our world braces for AI in every edge device, creating an urgent need for edge-AI SoCs. This SoC hardware needs to support high throughput, reliable and secure AI processing at Ultra Low Power (ULP), with a very short time to market. With its strong legacy in edge solutions and open processing platforms, the EU is well-positioned to become a leader in this SoC market. However, this requires AI edge processing to become at least 100 times more energy-efficient, while offering sufficient flexibility and scalability to deal with AI as a fast-moving target. Since the design space of these complex SoCs is huge, advanced tooling is needed to make their design tractable. The CONVOLVE project (currently in Inital stage) addresses these roadblocks. It takes a holistic approach with innovations at all levels of the design hierarchy. Starting with an overview of SOTA DL processing support and our project methodology, this paper presents 8 important design choices largely impacting the energy efficiency and flexibility of DL hardware. Finding good solutions is key to making smart-edge computing a reality.
