论文标题
量子优化的奇偶校验约束的低深度电路实施
Low-depth Circuit Implementation of Parity Constraints for Quantum Optimization
论文作者
论文摘要
我们提供了一个低门计数和深度电路的建筑，在使用奇偶校验映射时，在Qaoa中以plaquette形式的约束形式实现了三体和四体Pauli-Z产品运营商。这些电路可以在任何量子设备上实现，该量子设备在平方晶格上具有最接近的邻居连接，一次仅使用一种门类型和一个两倍的大门的方向。我们找到了与系统大小无关的电路深度的上限。该过程易于调整到特定于硬件的限制，例如同时执行门之间所需的最小空间距离，或者门仅在所有量子位的子集中同时可执行，例如一行。
We present a construction for circuits with low gate count and depth, implementing three- and four-body Pauli-Z product operators as they appear in the form of plaquette-shaped constraints in QAOA when using the parity mapping. The circuits can be implemented on any quantum device with nearest-neighbor connectivity on a square-lattice, using only one gate type and one orientation of two-qubit gates at a time. We find an upper bound for the circuit depth which is independent of the system size. The procedure is readily adjustable to hardware-specific restrictions, such as a minimum required spatial distance between simultaneously executed gates, or gates only being simultaneously executable within a subset of all the qubits, for example a single line.
