论文标题
通过MPI和电路开关FPGA网络的HPC挑战基准的多FPGA设计和缩放率
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks
论文作者
论文摘要
尽管FPGA加速器板及其各自的高级设计工具正在成熟，但仍然缺乏多FPGA应用程序，库，以及并非最不重要的一点，即基准和参考实现这些设备的HPC使用。就像在HPC中GPU的早期一样，对于可以合理地将其分解为松散耦合工作组的工作负载，可以通过使用主机上的MPI等标准通信接口来实现多加速器支持。但是，对于性能和生产力，某些应用程序可以从加速器的更紧密耦合中获利。 FPGA在将数据流特性扩展到其通信Intinterfaces时提供了独特的机会。在这项工作中，我们通过多FPGA支持扩展了HPCC FPGA基准套件，以及三个丢失的基准分析，这些基准特别是特征或压力间的设备间通信：B_EFF，PTRANS和LINPACK。通过使用Intel和Xilinx FPGA为当前董事会实施的所有基准测试，我们为多FPGA性能建立了基线。此外，对于以通信为中心的基准，我们探索了通过电路开关的FPGA网络直接FPGA到FPGA通信的潜力，该网络目前仅适用于其中一个董事会。在多达26个FPGA板上并行执行的评估使用了最大的学术FPGA装置之一。
While FPGA accelerator boards and their respective high-level design tools are maturing, there is still a lack of multi-FPGA applications, libraries, and not least, benchmarks and reference implementations towards sustained HPC usage of these devices. As in the early days of GPUs in HPC, for workloads that can reasonably be decoupled into loosely coupled working sets, multi-accelerator support can be achieved by using standard communication interfaces like MPI on the host side. However, for performance and productivity, some applications can profit from a tighter coupling of the accelerators. FPGAs offer unique opportunities here when extending the dataflow characteristics to their communication ininterfaces. In this work, we extend the HPCC FPGA benchmark suite by multi-FPGA support and three missing benchmarks that particularly characterize or stress inter-device communication: b_eff, PTRANS, and LINPACK. With all benchmarks implemented for current boards with Intel and Xilinx FPGAs, we established a baseline for multi-FPGA performance. Additionally, for the communication-centric benchmarks, we explored the potential of direct FPGA-to-FPGA communication with a circuit-switched inter-FPGA network that is currently only available for one of the boards. The evaluation with parallel execution on up to 26 FPGA boards makes use of one of the largest academic FPGA installations.
