论文标题
无同步数字链路控制器
Synchronizer-Free Digital Link Controller
论文作者
论文摘要
这项工作介绍了两个独立时钟域之间的生产者消费者链接。该链接允许通过对控制器电路指导的生产者和消费域的时钟频率进行轻微调整，从而实现无电竞争性，低延迟，高通量通信。任何这样的控制器均无法决定性地避免，检测或解决克服。通常，这是通过同步器来解决的，在控制环中产生了更大的死时间。我们遵循Friedrichs等人的方法。 （TC 2018）提出了含有竞争能力的电路。结果是一个简单的控制电路，它可能会变得不稳定，但决定性地避免了缓冲底底底或溢出。更具体地说，控制器输出可能会成为可稳定性，但这可能只会影响特定界限内的振荡器速度。相比之下，沟通可以保证保持不稳定性。我们正式证明了生产者消费者链接的正确性，并且可能只有很小的开销。通过对拟议实施的香料模拟，我们进一步证实了我们的主张。该模拟使用大约2GHz运行的65nm过程。
This work presents a producer-consumer link between two independent clock domains. The link allows for metastability-free, low-latency, high-throughput communication by slight adjustments to the clock frequencies of the producer and consumer domains steered by a controller circuit. Any such controller cannot deterministically avoid, detect, nor resolve metastability. Typically, this is addressed by synchronizers, incurring a larger dead time in the control loop. We follow the approach of Friedrichs et al. (TC 2018) who proposed metastability-containing circuits. The result is a simple control circuit that may become metastable, yet deterministically avoids buffer underrun or overflow. More specifically, the controller output may become metastable, but this may only affect oscillator speeds within specific bounds. In contrast, communication is guaranteed to remain metastability-free. We formally prove correctness of the producer-consumer link and a possible implementation that has only small overhead. With SPICE simulations of the proposed implementation we further substantiate our claims. The simulation uses 65nm process running at roughly 2GHz.
