论文标题
在有限场GF中使用多项式表示的序列形式乘数实现区域有效的VLSI实现（2M）
Area- Efficient VLSI Implementation of Serial-In Parallel-Out Multiplier Using Polynomial Representation in Finite Field GF(2m)
论文作者
论文摘要
有限字段乘法器主要用于误差校正代码和信号处理。有限的场乘数被认为是此类应用程序的瓶颈算术单元，它是有限场GF（2M）最复杂的操作，它需要大量的逻辑资源。在本文中，提出了一种新的修改序列化并行乘积算法，并提出了带交错的模块化还原的算法。与文献中提出的算法相比，提出的方法提供了有效的区域架构。降低的有限场乘数复杂性是通过在特定体系结构中利用逻辑NAND门来实现的。根据时间（延迟，关键路径）和空间（门斑点数）复杂性等标准评估所提出的体系结构的效率。详细的比较分析表明，基于逻辑NAND门的提议有限场乘数优于先前已知的结果
Finite field multiplier is mainly used in error-correcting codes and signal processing. Finite field multiplier is regarded as the bottleneck arithmetic unit for such applications and it is the most complicated operation over finite field GF(2m) which requires a huge amount of logic resources. In this paper, a new modified serial-in parallel-out multiplication algorithm with interleaved modular reduction is suggested. The proposed method offers efficient area architecture as compared to proposed algorithms in the literature. The reduced finite field multiplier complexity is achieved by means of utilizing logic NAND gate in a particular architecture. The efficiency of the proposed architecture is evaluated based on criteria such as time (latency, critical path) and space (gate-latch number) complexity. A detailed comparative analysis indicates that, the proposed finite field multiplier based on logic NAND gate outperforms previously known results
