论文标题
使用掺杂的硅浴缸 - 基于模拟和设备物理学的研究深入了解潜在的基于良好的纳米级FDSOI MOSFET：第二部分：可伸缩到10 nm栅极长度
Insight into Potential Well Based Nanoscale FDSOI MOSFET Using Doped Silicon Tubs- A Simulation and Device Physics Based Study: Part II: Scalability to 10 nm Gate Length
论文作者
论文摘要
PWFDSOI MOSFET中的掺杂硅区域（浴缸）通过减少载有OFF电流的载体数量，从而大大降低OFF电流。本文中介绍的对PWFDSOI MOSFET的模拟和设备物理研究的重点是该设备对10 nm栅极长度的可扩展性及其相关信息。在10 nm栅极长度PWFDSOI MOSFET中实现了7.6 x 10^5的高离子 /IOFF比为87 mV /十年。该研究是在具有未训练硅通道的设备上进行的。
The doped silicon regions (tubs) in PWFDSOI MOSFET cause significant reduction in OFF current by reducing the number of carriers contributing to the OFF current. The emphasis of the simulation and device physics study on PWFDSOI MOSFET presented in this paper is on the scalability of the device to 10 nm gate length and its related information. A high ION /IOFF ratio of 7.6 x 10^5 and subthreshold swing of 87 mV/decade were achieved in 10 nm gate length PWFDSOI MOSFET. The study was performed on devices with unstrained silicon channel.
