论文标题
迈向每秒通信：$ g_n $ -coset代码的高通量硬件实现
Toward Terabits-per-second Communications: A High-Throughput Hardware Implementation of $G_N$-Coset Codes
论文作者
论文摘要
最近，提出了$ g_n $ -coset代码的并行解码算法。该算法利用了两个等效的解码图。对于每个图，由独立组件代码组成的内部代码部分是并行解码的。获得代码位的外部信息，并在图形之间进行迭代交换，直到收敛为止。由于避免了串行的外代码处理，该算法比以前连续的取消算法具有更高的解码并行性。在这项工作中，我们提出了并行解码算法的硬件实现，它可以支持最大$ n = 16384 $。我们在TSMC $ 16NM $过程中完成解码器的物理布局，大小为$999.936μm\ times999.936μm，\，\，\ of 1.00mm^2 $。评估了解码器的面积效率和功耗，以$ n = 16384，k = 13225 $和$ n = 16384，k = 14161 $评估。该解码器的吞吐量超过$ 7NM $流程，高于$ 477Gbps/mm^2 $和$ 533GBPS/mm^2 $，带有五个迭代。
Recently, a parallel decoding algorithm of $G_N$-coset codes was proposed.The algorithm exploits two equivalent decoding graphs.For each graph, the inner code part, which consists of independent component codes, is decoded in parallel. The extrinsic information of the code bits is obtained and iteratively exchanged between the graphs until convergence. This algorithm enjoys a higher decoding parallelism than the previous successive cancellation algorithms, due to the avoidance of serial outer code processing. In this work, we present a hardware implementation of the parallel decoding algorithm, it can support maximum $N=16384$. We complete the decoder's physical layout in TSMC $16nm$ process and the size is $999.936μm\times 999.936μm, \,\approx 1.00mm^2$. The decoder's area efficiency and power consumption are evaluated for the cases of $N=16384,K=13225$ and $N=16384, K=14161$. Scaled to $7nm$ process, the decoder's throughput is higher than $477Gbps/mm^2$ and $533Gbps/mm^2$ with five iterations.
