论文标题
LLHD：硬件描述语言的多级中间表示形式
LLHD: A Multi-level Intermediate Representation for Hardware Description Languages
论文作者
论文摘要
现代硬件说明语言（HDL），例如SystemVerilog或VHDL，由于其纯粹的复杂性，不足以通过现代电路设计流进行运输。相反，每个设计自动化工具都将HDL降低到其自身的中间表示（IR）。这些工具是单片的，并且大多是专有的，在实施HDLS方面不同意，尽管存在许多冗余IRS，但如今没有IR可以通过整个电路设计流中使用。为了解决这个问题，我们提出了LLHD多级别IR。 LLHD的设计为简单，明确的参考描述，但完全捕获了现有的HDL。我们将参考编译器与完整CPU内核一样复杂的设计显示。 LLHD带有降低通行证到硬件NEAR结构IR，该结构IR很容易与现有工具集成在一起。 LLHD在没有冗余编译器或不相交的IRS的HDL和工具中建立了创新的基础。例如，我们实施了一个LLHD模拟器，该模拟器的运行速度比商业模拟器快2.4倍，但产生了同等的，周期级的结果。最初的垂直综合研究原型能够代表IR的所有级别，从行为降低到结构IR，并涵盖了足够的SystemVerilog子集以支持完整的CPU设计。
Modern Hardware Description Languages (HDLs) such as SystemVerilog or VHDL are, due to their sheer complexity, insufficient to transport designs through modern circuit design flows. Instead, each design automation tool lowers HDLs to its own Intermediate Representation (IR). These tools are monolithic and mostly proprietary, disagree in their implementation of HDLs, and while many redundant IRs exists, no IR today can be used through the entire circuit design flow. To solve this problem, we propose the LLHD multi-level IR. LLHD is designed as simple, unambiguous reference description of a digital circuit, yet fully captures existing HDLs. We show this with our reference compiler on designs as complex as full CPU cores. LLHD comes with lowering passes to a hardware-near structural IR, which readily integrates with existing tools. LLHD establishes the basis for innovation in HDLs and tools without redundant compilers or disjoint IRs. For instance, we implement an LLHD simulator that runs up to 2.4x faster than commercial simulators but produces equivalent, cycle-accurate results. An initial vertically-integrated research prototype is capable of representing all levels of the IR, implements lowering from the behavioural to the structural IR, and covers a sufficient subset of SystemVerilog to support a full CPU design.
